Solid-state dynamic random access memory (DRAM) is a cost-efficient bulk memory solution for many modern computing systems, including portable electronic devices. DRAM, including synchronous DRAM (SDRAM), offers a high bit density and relatively low cost per bit compared to faster, on-chip memory structures such as registers, static RAM (SRAM), and the like, and dramatically higher access speeds than electron, magneto-, or optical-mechanical bulk storage such as hard disks, CD-ROMs, and the like.
FIG. 1 depicts a logical view of a representative 512 Mbit DRAM array 100. The array 100 is organized as a plurality of separately addressable banks 102, 104, 106, 108. Each bank is divided into a large number, e.g., 4096, of rows 110. Each row 110 is divided into a plurality of columns (e.g., 512 columns), and each column includes a number of data bits, typically organized as bytes (e.g., 8 bytes). Several data addressing schemes are known in the art. For example, in Bank, Row, Column (BRC) addressing, a memory address may be interpreted as
31-2625-2423-1211-32-0ChipBankRow selectColumn selectByteselectselectselectIn an alternative addressing scheme such as Row, Bank Column (RBC) addressing, the memory address may be interpreted as
31-2625-1413-1211-32-0ChipRow selectBankColumn selectByteselectselectselect
DRAM memory arrays are volatile; data stored in a DRAM array must be refreshed periodically to maintain its integrity. During a DRAM refresh operation, a large number of data storage locations are simultaneously read out of the array 100 and recharged. Conventionally, DRAM arrays are refreshed row-by-row. That is, a row—or, in some implementations, the same row simultaneously in every bank—is selected and all data within the row are refreshed in a single operation. As used herein, the term “independently refreshable memory unit,” or IRMU, refers to the quantum of data that is refreshed in a single refresh operation. The IRMU for a DRAM array is typically a row, although the present invention is not limited to row-by-row refresh operations.
Refresh operations directed to a IRMU are conventionally interspersed with memory accesses, and are timed such that the entire DRAM array is refreshed prior to any data being lost due to charge decay. Traditionally, the refresh addresses—that is, the address of each independently refreshable memory unit—are supplied by a memory controller, such as a processor, which specifies a refresh operation through a unique combination of control signals. Modern SDRAM components may include two additional refresh modes: self-refresh and auto-refresh. In both modes, the SDRAM component includes an internal refresh address counter. Self-refresh is utilized in many systems, such as battery-powered electronic devices, that employ a “sleep” mode to conserve power. In self-refresh mode, the SDRAM component is not accessible to store or retrieve data; however, the SDRAM performs refresh operations internally to ensure the integrity of stored data. In auto-refresh mode, the memory controller specifies a refresh operation, but does not provide a refresh address. Rather, the SDRAM component increments an internal refresh address counter, which provides successive independently refreshable memory unit (e.g., row) addresses.
Each refresh operation consumes power as data are read from the DRAM array and recharged. However, particularly following power-on or a system reset, most memory storage locations in the DRAM array do not contain valid data.